As integrated circuits continue to scale downward in size, the FinFET is still an attractive device for use in semiconductor integrated circuits (ICs). With FinFETs, as with other transistor types, contacts that connect to the source, drain, and gate of the transistor to other structure are an important factor in the production of reliable integrated circuits with desired performance characteristics. FinFETs in a vertical configuration (vertical FinFETs) are a strong candidate for potentially extending current semiconductor technology to its scaling limits. For example, with an excellent performance/area ratio, gate-all-around vertical FinFETs are particularly strong candidates for making, for instance, highly dense static random access memory (SRAM) cells for semiconductors. However, in conventional vertical FinFET devices, the cell height is quite tall thereby impacting scalability, and gate contact placement is typically restricted to the middle of the cell located over the isolation region which limits routing flexibility (e.g., only metal lines in a vertical direction can be used for gate contact signals). Without more gate contact placement flexibility and reduced cell height, scaling down to smaller technology nodes, such as 7, 5 and 3 nanometer technologies and beyond, may not be successful.